Electronic components and devices, such as microprocessors and other various integrated circuits, have advanced in many significant ways. As one example, feature sizes have moved into the sub-micron range thereby allowing larger numbers of transistors to be formed on a given silicon surface area. This, in turn, has resulted in greater device and circuit density on the individual chips. As another example, in part due to the first advance discussed above, microprocessors have increased dramatically in clock speed. At present, microprocessor speeds of 2.5 Gigahertz are coming to market and the 3 and 4 Gigahertz range is rapidly being approached.
Because of the advances in device density and microprocessor speed discussed above, it is now important to minimize any potential delays in the processing of information and to recognize that existing circuits that once operated within tolerable margins may, at the higher clock speeds of newer systems, become the limiting factor in microprocessor performance.
One example where higher clock speeds have made prior art circuits and methods inadequate is in the area of memory arrays and, in particular, on-chip memory arrays in microprocessors. FIG. 1 shows a typical prior art memory array 100 including: write amplifier block 101; write column switch 103; bitline pre-charge circuit 105 and memory cells 110, 120, and 130 coupled between bitline pair 107 and 109.
The structure and operation of prior art memory arrays, such as prior art memory array 100, is well known to those of skill in the art and is therefore not discussed in more detail herein to avoid detracting from the present invention.
As shown in FIG. 1, and as is also well known to those of skill in the art, each of memory cells 110, 120, and 130 of prior art memory array 100 included an inherent parasitic capacitance, and bitlines 107 and 109 also include an inherent parasitic capacitance and an inherent resistance. These parasitic capacitances and resistances are shown in FIG. 1 symbolically as parasitic capacitors 111, 115, 121, and 125 and resistors 113, 117, 123 and 127.
A pair of parasitic capacitances, such as capacitors 111, 115, associated with memory cell 110 and bitlines 107 and 109, and an inherent resistance, such as resistors 113, 117, also associated with memory cell 110 and bitlines 107 and 109, are an unavoidable component of each memory cell added to bitline pair 107/109. Consequently, the more memory cells, such as memory cells 110, 120 and 130, that are coupled to bitline pair 107/109, the greater the cumulative parasitic capacitance and resistance there is at end 150 of bitline pair 107/109.
Unfortunately, modern electronic devices are typically requiring larger and higher density memory designs. Consequently, there can be a requirement to increase the number of memory cells connected to a bitline in order to keep a balance between wordline and bitline loads. In addition, to meet a given aspect ratio of a memory array, a designer may need more memory cells to be connected to a bitline. As a result, very long or “tall” bitlines that are very heavily loaded for parasitic resistance and capacitance result.
As noted above, this becomes a problem because, for example, during a write operation, the switching rate of the heavily RC loaded bitlines will be very low, and, as a result, the end of the bitlines, such as end 150 of bitline pair 107/109, may not have time to discharge to a value very close to zero, also called a digital zero or “ground” in the time allotted by the system clock before the next operation. It is important that the bitline discharge to this value very close to zero to ensure that there is enough margin to write to the memory array at the given frequency. As a result, the speed of operation of the memory array, and the entire system, is often slowed down. Of course, as the speed of system clocks increases, this problem becomes even more pronounced as there is even less time between operations for a bitline to discharge from a pre-charged value. In addition, as more and more memory is moved into “on chip” caches, the problem becomes even more immediate and more pronounced because these on-chip memory arrays are expected to operate at even higher speeds than off-chip designs.
To overcome the problems described above with respect to prior art memory array 100, a designer could try adding a an additional write driver, such as write drive block 101 in FIG. 1, in association with additional write column switch 103, to end 150 of prior art memory array 100. This action would effectively cut the number of memory cells on a bitline/bitline pair in half. However, this solution requires more components, uses more precious silicon space and often complicates the design by adding more control signals, routing metal, and synchronization issues. Another method would be to increase the width of bitlines 107 and 109. However, this “solution” would also use more silicon space and would add even more parasitic capacitance to bitlines 107 and 109.
As noted, in the prior art, there were typically fewer memory cells per bitline, the system clock speeds were slower and memory arrays were typically off-chip. However, with the advances discussed above regarding clock speeds and the ability to put more memory on-chip, the prior art memory arrays and methods are rapidly proving inadequate to need the needs of modern electronic systems and devices.
What is needed is a circuit and method for boosting bitline performance that allows long bitlines, with large numbers of memory cells attached, to discharge to a digital zero in a faster time and does not require a significant number of added components, does not require multiple control signals, and takes up minimal additional silicon area.